As telecommunication devices and personal digital assistants increase in popularity so do their demand for new and interesting features. Such features may include digital video communication, or imbedded image capture apparatus. One device that may assist in the creation of this feature is the CMOS image sensor.
A CMOS image sensor is a semiconductor device that contains an array of light sensitive pixel elements arranged in rows and columns, for the conversion of light energy into an electrical signal. Also, digital signal processing circuitry may be integrated onto the same die as the CMOS image sensor, allowing the reduction in size of the amount of peripheral circuitry needed to interface with the image sensor. As well, CMOS image sensors and the processing circuitry can be manufactured using current standard CMOS fabrication techniques, giving it a significant cost advantage over using the alternative CCD (charge coupled device) image sensor which requires special manufacturing techniques.
There are different types of pixel structures that can be used in a CMOS imager. One of these is a 3T (three-transistor) pixel, an example of which is shown in FIG. 1. Typically, a read cycle is initiated by applying a pulse of the reset signal RSTi to reset transistor 106 to set node A to a known voltage. The integration begins once the reset pulse is completed. The photodiode 104 is exposed to light 103 and discharges node A at a given rate depending on the intensity of the light 103. As node A is being discharged, a source follower transistor 102 amplifies the node A voltage onto node B. Once the integration is completed and node A is appreciably discharged, the row access signal RAi pulses and activates the row access transistor 108. This allows the amplified voltage on node B to be dumped onto the column 109, where it is amplified and sent through a column data path. From the data path, the data is then processed by signal processing circuitry either on or off the chip.
An example of a column amplifier stage is shown in FIG. 2. The column amplifier stage includes an operational amplifier 206, capacitors 202 and 205 and transistors 210, 212 and 204. The column bit-line COLj is connected to the source of transistor 210. The column amplifier stage read sequence is described in conjunction with FIG. 3. Prior to the row access pulse, during the integration stage, the Column Access signal CA is a logical low. Once the row is accessed, the row access pulse RAi is a logical high and the source follower 102 drives the column line 109 to its video signal level. During this time the sampling capacitor 202 and the feedback capacitor 205 are set to a reference voltage VREF. Then the Direct Readout signal DRO switches to a logical low followed by the Column Access signal CA which switches to a logical high. From this point in time, the video level of the column line COLj is being sampled. Then the Column Reset signal CRS switches to a logical low followed by the Column Access signal CA which switches to a logical low. After Direct Readout signal DRO switches to a logical high the output voltage VOUTj becomes valid until the Column Reset signal CRS switches to a logical high.
The read sequence described above and illustrated in FIG. 3 has some inherent deficiencies. Throughout the array of pixel elements there will be variations in the device characteristics due to variations in the device processing. For example the threshold voltage of transistor 106 in FIG. 1 may vary across the array causing the reset voltage to be at different levels in the pixels from column to column and row to row. Any of the devices in the pixel and/or column current source 214 in FIG. 2 can have these variations as well. A known method has been developed in the industry to alleviate this problem. The method, referred to as double sampling, is used to measure the difference between the reset voltage and the integrated voltage. In this way, the device variation is subtracted. Double Sampling (DS) requires a normal read sequence as was shown in FIG. 3 with an additional reset pulse at the end of the integration time. When using a double sampling technique the subtraction is done after the integrated photodiode voltage has been sampled. A timing sequence for double sampling is shown in FIG. 4. Details of the double sampling method is well known and will not be further described here.
The frame rate for a CMOS sensor array is one of the most critical figures of merit. The frame rate is the speed by which an entire array of pixels can be read. Typically an entire row of pixels can be reset, integrated and read out in parallel.
When an entire imaging array is to be read, there are at least two methods that can be used. The slower of the two methods uses a row by row technique where the entire timing cycle as shown in FIGS. 3 and 4 are completed before the sequence begins on the next row, which is not necessarily adjacent. The frame rate tFRAME1 is then limited to the time tRESET required to reset, the time tINT required to integrate, the time tREAD required to read each row and the time tHB (known as horizontal blank time) required to switch to the next row multiplied by the number NROWS of rows of the entire array. Or, in other words:tFRAME1=NROWS×(tRESET+tINT+tREAD+tHB)  (Equation 1)In most circumstances, the integration time tINT is significantly longer then the reset time tRESET, the read time tREAD and the horizontal blank time tHB.
A faster technique, known in the industry as a “rolling shutter”, is illustrated in FIG. 5. The technique involves overlapping the resets of later rows with respect to the integration of earlier rows. For example, reset pulse 503 for row Rj+1 occurs during the integration period of the pixels in row Rj, reset pulse 505 for row Rj+2 occurs during the integration period of the pixels in row Rj+1, reset pulse 507 for row Rj+3 occurs during the integration period of the pixels in row Rj+2, and so on for the remaining rows N. The time needed to readout the entire frame is significantly reduced due to the overlapping of the inter-row read sequences and is quantified by:tFRAME2=NROW×tROW  (Equation 2)where tROW=tREAD+tHBEquation 2 does not include the period of time tRST+tINT which will occur as the first row of pixels is being reset and integrated before the reading of any pixels takes place.
Since the integration time tINT is usually much greater than the read time tREAD, in most cases we can achieve a much higher frame rate. In fact in some situations it is possible to achieve up to an order of magnitude of improvement. As can be seen in FIG. 5 for example, the resetting of each subsequent row now takes place after four units of time rather then 11 units of time. The minimum time between the resetting of row of pixels will be tROW=tREAD+tHB after the resetting of the preceding row.
This type of frame read sequence could be achieved by addressing the row reset and read lines independently with the use of two separate counters. This type of architecture is described in FIG. 6. The Reset Address Counter 610 receives external signals (not shown) that define a set number of row addresses to proceed through in the 3T CMOS sensor array 609. The Reset Address Counter 610 then sends the addresses in sequence to the Reset Decoders 605, via the Reset Address signal (RSTAXk) lines 603. The Reset Decoders 605 then activate the n Reset Drivers 612, which then activate the corresponding Reset signal RSTi lines 607, in accordance with the sequence of input addresses and a Reset Enable signal rst—en.
The Read Access Address Counter 611 also receives external signals (not shown) that define a set number of row addresses to proceed through in the 3T CMOS sensor array 609. The Read Access Address Counter 611 then sends the addresses in sequence to the Row Decoders 606, via the Row Access Address signal (RAAXk) lines 604. The Row Decoders 606 then use that information to activate the corresponding Row Drivers 613, which in turn activate the appropriate Row Access signal RAi lines 608, in accordance with the sequence of input addresses and a Row Access Enable signal, ra—en.
There are a number of problems associated with the architecture described in FIG. 6, in particular when the array is to be read using double sampling. An embodiment of a double sampling technique is described in U.S. patent application Ser. No. 09/886,598 filed on Jun. 21, 2001, which is incorporated herein by reference. The read circuitry associated with the array 609 cannot necessarily change the reset addresses to perform a double sample reset. For instance, the second reset 502, 504, 506 on an earlier row may not be possible because a later row may be using that address to perform a pre-integration reset 503, 505, 507 as illustrated in FIG. 5. As shown in the FIG. 1, the potential overlap of a pre-integration reset with a double sampling reset depends upon the integration time used in reading the array.
It is desirable to be able to vary integration time of the array, as the integration time partially determines the output voltage of a pixel element. It is possible to avoid the above mentioned overlap and maintain an integration time that is variable using three methods known in the industry. The first method is to simply read out each row one at a time without using any overlap as already mentioned in the above text. However this method is not desirable, as it is extremely slow.
The second method requires a detailed understanding of the pixel array timing, wherein the use of potentially overlapping integration times are simply avoided through the use of a third set of addresses used explicitly for the double sampling reset address signal. However this method is not desirable as it is complex, and restricts the use of specific integration times that may be desirable.
The third method involves using shift registers to control the row reset and row access signals, instead of a binary decode method. However, using shift registers requires additional wait time to acquire sub-windows in particular parts of the array, as opposed to the random access functionality a binary decode method yields.
Therefore, there is a need for a new method that solves the problem of the first reset pulse in one row overlapping with the second reset pulse in a previous row. It is also desirable that this new method has a fast frame rate, is not overly complex in regards to timing or hardware, does not restrict the potentially available integration times and benefits from random accessibility.